Intellectual Property India Publishes Patent Application for 'Low-Power 4X4 Mesh Network-On-Chip With Power-Gating And Clock-Gating' Filed by Vellore Institute Of Technology

MUMBAI, India, Jan. 2 -- Intellectual Property India has published a patent application (202541122837 A) filed by Vellore Institute Of Technology, Vellore, Tamil Nadu, on Dec. 5, 2025, for 'low-power 4x4 mesh network-on-chip with power-gating and clock-gating.'

Inventor(s) include Dr. Ragunath G; and Mr. Jalagari Pavan Karthik.

The application for the patent was published on Jan. 2, under issue no. 01/2026.

According to the abstract released by the Intellectual Property India: "The present disclosure provides a Network-on-Chip system (500) having a mesh topology with routers arranged in rows and columns. Each router includes a buffer module for storing incoming data packets, an arbitration logic module for determining output ports based on packet headers, power-gating circuitry with sleep transistors (546) for disconnecting idle components from power supply during inactivity, clock-gating circuitry (538) for halting clock signals to inactive modules, and a power control system for monitoring activity and managing power state transitions. The mesh topology includes a 4x4 configuration with sixteen routers (504, 512, 520, 528) in four rows and columns, where each router has a unique 4-bit address with 2 bits for row and column identification. The buffer module includes a four-entry First-In-First-Out buffer (506, 514, 522, 530), and the arbitration logic module includes a 4:1 multiplexer for generating selection signals."

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