MUMBAI, India, Feb. 6 -- Intellectual Property India has published a patent application (202631010860 A) filed by C. V. Raman Global University, Bhubaneswar, Orissa, on Feb. 2, for 'load frequency control by speed governors of twoarea power system using digital controller with deadbeat approach.'
Inventor(s) include Prof. Kartik Chandra Patra; and Dr. Asutosh Patnaik.
The application for the patent was published on Feb. 6, under issue no. 06/2026.
According to the abstract released by the Intellectual Property India: "This invention relates to Load Frequency Control (LFC) in two-area interconnected power systems utilizing digital controllers with deadbeat approach. The present invention addresses the critical problem of limit cycles (LC) caused by governor backlash nonlinearities, which degrade power system stability and performance. Conventional LFC schemes using traditional governors suffer from self-sustained oscillations that threaten grid stability and operational reliability. The Digital Deadbeat Controller (DDC) formulated and implemented herein provides an instantaneous response at t=0 that is completely transient-free, ripple-free, and exhibits zero steady-state error. This revolutionary approach enables real-time application in LFC schemes, ensuring effective grid regulation and maintaining power system stability within minimum possible time. The deadbeat controller eliminates the requirement for steady-state error elimination, provides perfect command tracking, and eliminates the effects of constant disturbances with finite settling time. The implementation of DDC in LFC scheme represents the first-time application of this approach in the existing literature, demonstrating superior performance metrics including faster response time, better transient response, improved stability margins, and enhanced overall system reliability. Simulation results validate the effectiveness of the proposed approach in suppressing limit cycles and maintaining frequency stability in two-area power systems."
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