MUMBAI, India, Jan. 9 -- Intellectual Property India has published a patent application (202541110752 A) filed by Rama Krishna Pasupuleti, Suryapet, Telangana, on Nov. 13, 2025, for 'k and r constant framework for computational optimization in semiconductor and vlsi design.'
Inventor(s) include Rama Krishna Pasupuleti.
The application for the patent was published on Jan. 9, under issue no. 02/2026.
According to the abstract released by the Intellectual Property India: "This work presents a novel framework applying K (scaling) and R (reduction) constants to semiconductor and VLSI architectures. The constants are used to dynamically optimize transistor switching efficiency, interconnect routing, and logical gate utilization, leading to enhanced speed, reduced power consumption, and minimal signal delay. The K constant defines the proportional scaling of computational or electrical load, while the R constant quantifies reduction in redundant transitions or data propagation. Together, they establish an adaptive mathematical control model within chip design. I The framework is applicable across ASICs, SoCs, PPG A architectures, and CMOS layouts, providing a unified optimization layer that bridges mathematical computation with electronic design automation (EDA), All mathematical derivations, circuit models, simulation results, and code implementations (Python, MATLAB, Verilog) are original, forming the core patentable material."
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