MUMBAI, India, Aug. 22 -- Intellectual Property India has published a patent application (202517053736 A) filed by Advanced Micro Devices, Inc., Santa Clara, U.S.A., on June 3, for 'inclusion of dedicated accelerators in graph nodes.'

Inventor(s) include Chajdas, Matthus G.; Mantor, Michael J.; Mccrary, Rex Eldon; Brennan, Christopher J.; Martin, Robert; and Bennett, Brian Kenneth.

The application for the patent was published on Aug. 22, under issue no. 34/2025.

According to the abstract released by the Intellectual Property India: "Systems, apparatuses, and methods for implementing a hierarchical scheduling in fixed-function graphics pipeline are disclosed. In various implementations, a processor includes a pipeline comprising a plurality of fixed-function units and a scheduler. The scheduler is configured to schedule a first operation for execution by one or more fixed-function units of the pipeline by scheduling the first operation with a first unit of the pipeline, responsive to a first mode of operation and schedule a second operation for execution by a selected fixed-function unit of the pipeline by scheduling the second operation directly to the selected fixed-function unit, independent of a sequential arrangement of the one or more fixed-function units in the pipeline, responsive to a second mode of operation."

The patent application was internationally filed on Nov. 27, 2023, under International application No.PCT/US2023/081181.

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