MUMBAI, India, Jan. 2 -- Intellectual Property India has published a patent application (202541122910 A) filed by Vellore Institute Of Technology, Vellore, Tamil Nadu, on Dec. 5, 2025, for 'hybrid arithmetic logic unit with integrated fused multiply-add unit.'
Inventor(s) include Dr. Ravi S; and Ms. Vennila.
The application for the patent was published on Jan. 2, under issue no. 01/2026.
According to the abstract released by the Intellectual Property India: "The present disclosure provides a hybrid arithmetic logic unit comprising an integer unit configured to perform integer arithmetic operations, a floating-point unit configured to perform floating-point arithmetic operations, a fused multiply-add unit integrated within the floating-point unit and configured to perform operations of the form a b+c in a single computational step with single rounding, a control unit comprising an opcode decoder configured to dynamically select between the integer unit and floating-point unit based on instruction type, and a shared data path connecting the units. The shared data path enables resource reuse and reduces hardware redundancy. The fused multiply-add unit comprises a carry-save array multiplier configured to generate partial products in parallel, a Brent-Kung adder configured to perform final summation with logarithmic delay characteristics, and a leading zero anticipator configured to predict normalization shift requirements for reducing processing latency."
Disclaimer: Curated by HT Syndication.
