Intellectual Property India Publishes Patent Application for 'High Speed Interfaces In Lower Technology Node Siliconisation (HSINLTS)' Filed by Primesoc Technologies Llp

MUMBAI, India, Feb. 13 -- Intellectual Property India has published a patent application (202541125534 A) filed by Primesoc Technologies Llp, Bangalore, Karnataka, on Dec. 12, 2025, for 'high speed interfaces in lower technology node siliconisation (hsinlts).'

Inventor(s) include Jebaselvi J.

The application for the patent was published on Feb. 13, under issue no. 07/2026.

According to the abstract released by the Intellectual Property India: "Any electronic products has silicon chip inside. To get silicon out of foundry, involves millions of dollars expenses especially when it comes to high speed interfaces. In order to optimise the cost required for siliconisation, this invention lists an architecture which can be used to productise. BRIEF DESCRIPTION OF DRAWINGS: Fig. 1: We propose the above architecture which differentiates soft IP digital controller in silicon and transceiver with glue logic in FPGA. : Same as above fig, but glue logic in separate silicon chip We propose the above architecture which differentiates soft IP digital controller in silicon1, glue logic in silicon2 and transceiver in FPGA."

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