MUMBAI, India, Jan. 9 -- Intellectual Property India has published a patent application (202541112337 A) filed by Dr. Suvitha S; and S. A. Engineering College, Chennai, Tamil Nadu, on Nov. 17, 2025, for 'high-performance 32-bit risc-v alu architecture integrating brent-kung parallel prefix adder and ved.'
Inventor(s) include Dr. Suvitha S.
The application for the patent was published on Jan. 9, under issue no. 02/2026.
According to the abstract released by the Intellectual Property India: "The present invention relates to a high-performance 32-bit Arithmetic Logic Unit (ALU) architecture designed for integration within a RISC-V processor core, aimed at improving 17-Nov-2025/116794/202541112337/Form 2(Title Page) computational speed, power efficiency, and silicon area utilization. The ALU incorporates a Brent-Kung Parallel Prefix Adder and a Vedic Multiplier based on the Urdhva Tiryagbhyam algorithm to optimize arithmetic performance. The Brent-Kung adder minimizes logic depth and wiring complexity, resulting in reduced propagation delay and area requirements. The Vedic multiplier performs simultaneous partial product generation and accumulation, enabling faster and more efficient multiplication operations. The integration of these arithmetic modules within the RISC-V pipeline provides enhanced instruction execution speed, reduced latency, and efficient resource allocation while maintaining architectural simplicity. Hardware implementation and synthesis using the Xilinx Vivado Design Suite demonstrate significant improvements in delay, power, and area compared to conventional ALUs employing ripple-carry adders and array multipliers. The disclosed architecture delivers superior computational throughput, low power dissipation, and minimal latency, making it suitable for high-performance embedded processors, digital signal processing units, and real-time computing applications."
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