MUMBAI, India, July 11 -- Intellectual Property India has published a patent application (202521059300 A) filed by National Institute Of Technology, Raipur, Chhattisgarh, on June 20, for 'hardware encryption system for tinyjambu lightweight cipher using fusionx area efficient architecture.'
Inventor(s) include Pankaj Ku Choubey; Dr. Bibhudendra Acharya; Dr. Bijayananda Patnaik; and Dr. K Abhimanyu Kumar Patro.
The application for the patent was published on July 11, under issue no. 28/2025.
According to the abstract released by the Intellectual Property India: "The present invention discloses a hardware system (100) for implementing a lightweight authenticated encryption algorithm, such as TinyJAMBU, on an FPGA. The system comprises a configurable data input interface (101) for accepting 128-bit or 192-bit keys, 32-bit or 64-bit messages and associated data, and a 96-bit nonce. A unified selection logic unit (102) provides input selection signals for key, message, associated data, and clock/reset. A controller (103) governs initialization, key/nonce setup, data processing, and encryption phases, routing inputs via selection signals (Ksel, Msel, ADsel, Fsel) to the algorithmic data logic unit (107). The algorithm executes cryptographic functions using nonlinear feedback shift registers and permutation-based mixing. A state update module (104) and counter module (105) work in synchronization via a gated clock. The output interface (106) generates 32/64-bit ciphertext and a 64-bit authentication tag, dynamically formatted based on input widths."
Disclaimer: Curated by HT Syndication.
