MUMBAI, India, May 29 -- Intellectual Property India has published a patent application (202641041837 A) filed by Chennai Institute Of Technology, Chennai, Tamil Nadu, on April 1, for 'hardware efficient fir filter design based on optimized truncated multiplier and optimized mux- based adder architecture.'
Inventor(s) include Dr. S. Murugeswari Murthy; Dr. R. Suresh Kumar; T. Sampath; and J. Eric Clapten.
The application for the patent was published on May 29, under issue no. 22/2026.
According to the abstract released by the Intellectual Property India: "The titled invention discloses a digital FIR filter for low area, low power and high-speed DSP application. In the transposed form FIR filter (1) the Multiplication and Accumulation (MAC) unit (2) is designed using regular truncated Multiplier (3) with normal full adder. This conventional FIR filter architecture results in more delay, more power utilization and more area. To overcome this disadvantage, the proposed architecture of the FIR filter MAC unit is designed with truncated multiplier (3) having mux based full adder (6). The full adder is designed using 4:1 mux and applied in the truncated multiplier (3) and this multiplier is used to implement a high-performance FIR filter. The proposed FIR filter is synthesized and implemented u^ng XilinxJSE 10.1 and Spartan III FPGA xc3s50 device."
Disclaimer: Curated by HT Syndication.
