MUMBAI, India, May 29 -- Intellectual Property India has published a patent application (202631036812 A) filed by Mr. Jyotiprakash Mishra, Bhubaneswar, Odisha, on March 26, for 'hardware-accelerated microarchitectural event classifier with programmable feature extraction pipeline and on-chip ensemble inference engine for real-time malware detection in risc-v processors.'
Inventor(s) include Mr. Jyotiprakash Mishra; Prof. Sanjay K. Sahay; Ms. Swati Mishra; and Mr. Aman Pathak.
The application for the patent was published on May 29, under issue no. 22/2026.
According to the abstract released by the Intellectual Property India: "A hardware-accelerated malware detection system (100) for RISC-V processors comprising a Continuous Event Capture Unit (200) that monitors Hardware Performance Counter values through a direct hardware tap interface at cycle-level granularity, a Pipelined Feature Extraction Engine (300) implementing a five-stage hardware pipeline computing mean, variance, skewness, kurtosis, and Shannon entropy from event count windows using fixed-point arithmetic, an On-Chip Ensemble Inference Engine (400) implementing a Random Forest classifier with 64 parallel decision trees stored in programmable SRAM and traversed simultaneously by dedicated Tree Traversal Units (420) with majority vote aggregation (430), and an Adversarial Resilience Monitor (500) using CUSUM change-point detection (510) and instruction-event correlation analysis (520) to detect attempts to manipulate HPC profiles. The system achieves zero CPU overhead, microsecond-level detection latency, and continuous monitoring without software sampling gaps. A Linux Kernel Security Module (600) loads trained models, configures detection parameters, handles detection interrupts, and enforces configurable response policies. The invention provides tamper-resistant malware detection suitable for resource-constrained IoT deployments on RISC-V processors."
Disclaimer: Curated by HT Syndication.
