MUMBAI, India, Sept. 5 -- Intellectual Property India has published a patent application (202441011932 A) filed by Samsung Electronics Co. Ltd., Gyeonggi, Republic of Korea, on Feb. 20, 2024, for 'full adder circuit and methods for high speed computing applications.'
Inventor(s) include Mitesh Goyal; Mayuresh Dhanawade; Abhishek Ghosh; Utkarsh Garg; and Vinod.
The application for the patent was published on Sept. 5, under issue no. 36/2025.
According to the abstract released by the Intellectual Property India: "Full Adder circuit and methods for high speed computing applications A Full Adder (FA) circuit (600) includes a Carry Output Generation (COG) circuit (602) including a first set of inverter gates (606) to generate inverted input signals, and AND gates (608) connected to the first set of inverter gates (606) to generate a first output signal from the inverted input signals. An OR gate (610) is connected to the AND gates (606), and a second inverter gate (612) is connected to the OR gate (610). The OR gate (610) generates a second output signal from the first output signal, and the second inverter gate (612) generates a Carry Output (CO) signal from the second output signal. A Sum Generation (SG) circuit (604) is connected to the COG circuit (602) to generate an output SUM signal."
Disclaimer: Curated by HT Syndication.
