MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641049571 A) filed by Srinivasa Ramanujan Institute Of Technology; Mr. Y. Madhusudhana; T. Pallavi; Y. Bhavya; and V. Karthikeya, Ananthapuramu, Andhra Pradesh, on April 18, for 'fpga implementation of multipliers using reversible logic gates.'
Inventor(s) include Srinivasa Ramanujan Institute Technology; Mr. Y. Madhusudhana; T. Pallavi; Y. Bhavya; and V. Karthikeya.
The application for the patent was published on May 1, under issue no. 18/2026.
According to the abstract released by the Intellectual Property India: "Power dissipation and delay are major challenges in modern VLSI systems, particularly in arithmetic units used for Digital Signal Processing (DSP) and Multiply-Accumulate (MAC) operations. Reversible logic has emerged as an effective solution to reduce energy loss by eliminating information destruction during computation. However, most existing reversible multiplier architectures support only unsigned operations and suffer from increased delay and hardware complexity when extended to signed arithmetic due to runtime sign-extension logic. In this paper, a configurable signed multiplier based on reversible logic is proposed using a precoded two's complement technique. The sign of the operands is processed prior to multiplication, allowing partial product generation to be performed on magnitude values and thereby reducing critical path delay and reversible logic overhead. Zero detection encoding is incorporated to avoid redundant computations, further optimizing garbage outputs and constant inputs. The proposed architecture supports configurable signed and unsigned operation, making it suitable for reconfigurable and FPGA-based DSP systems. Qualitative analysis demonstrates that the proposed design offers improved flexibility, reduced delay, and optimized hardware complexity compared to existing reversible multiplier designs."
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