MUMBAI, India, March 14 -- Intellectual Property India has published a patent application (202514059956 A) filed by Kyosan Electric Mfg. Co. Ltd., Kanagawa, Japan, on June 23, 2025, for 'fail-safe computer system.'
Inventor(s) include Anzawa Takuya; Itagaki Tomonori; and Oki Yuji.
The application for the patent was published on March 13, under issue no. 11/2026.
According to the abstract released by the Intellectual Property India: "In a fail-safe computer system (1), a master CPU (12) determines and assigns, for each assignment program, a priority processing CPU and a reserve processing CPU to be in charge of calculation processing of the assignment program, transmits given input data for the assignment program to the priority processing CPU and the reserve processing CPU to which the assignment program is assigned, causes the priority processing CPU and the reserve processing CPU to execute calculation processing based on the input data subsequent to a previous calculation process, and obtains calculation result data . The priority processing CPU executes the calculation processing based on the input data, and transmits the calculation result data to the master CPU (12) and the reserve processing CPU. The reserve processing CPU executes the calculation processing based on the input data, and transmits the calculation result data to the master CPU (12)."
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