Intellectual Property India Publishes Patent Application for 'Enhanced Five-Stage Pipelined Risc-V Processor With Integrated Iot-Based Hazard Mitigation System' Filed by Bhavya Gautam; and Dr Mithileysh Sathiyanarayanan

MUMBAI, India, May 29 -- Intellectual Property India has published a patent application (202611053021 A) filed by Bhavya Gautam; and Dr Mithileysh Sathiyanarayanan, New Delhi, on April 25, for 'enhanced five-stage pipelined risc-v processor with integrated iot-based hazard mitigation system.'

Inventor(s) include Bhavya Gautam; and Dr Mithileysh Sathiyanarayanan.

The application for the patent was published on May 29, under issue no. 22/2026.

According to the abstract released by the Intellectual Property India: "The invention relates to a 32-bit RISC-V compatible processor implementing a five-stage pipeline architecture (instruction fetch, instruction decode, execution, memory access, and writeback) with an integrated IoT-based hazard detection and resolution unit that concurrently monitors pipeline dependencies and selectively applies data forwarding or pipeline stalling to mitigate 360 hazards. The system comprises forwarding paths from execution and memory stages to bypass writeback delays for dependent operands, load-use hazard detection logic that inserts mandatory stalls when forwarding cannot satisfy dependencies, and early branch resolution mechanisms integrated in the execution stage that enable single-cycle branch penalties through immediate pipeline flush operations. FPGA-optimized microarchitectural features reduce hardware resource consumption to 2,500-3,500 LUTs and 1,200-1,800 FFs while maintaining 50-100 MHz clock frequencies. A modular extension interface facilitates integration of custom instructions for domain-specific acceleration including cryptographic, signal processing, and machine learning operations. The present invention ensures reduced pipeline stall cycles, improved instructions per cycle performance (0.7-0.85 IPC), and maintains architectural simplicity suitable for embedded systems, educational applications, and customizable computing platforms, while providing comprehensive hazard mitigation capabilities not found together in existing RISC-V processor implementations."

Disclaimer: Curated by HT Syndication.