MUMBAI, India, Feb. 27 -- Intellectual Property India has published a patent application (202641019388 A) filed by Dr C Pakkiraiah, Chittoor, Andhra Pradesh, on Feb. 19, for 'encrypt/decrypt module: design of energy efficient modular multiplier architecture.'

Inventor(s) include Dr C Pakkiraiah; Dr Thirumalesu K; Dr Syed Fazruddin; Dr. P Anil Kumar; Dr. A. Divya; and Dr Avvaru Subramanyam.

The application for the patent was published on Feb. 27, under issue no. 09/2026.

According to the abstract released by the Intellectual Property India: "The development of arithmetic-functioning circuits constitutes one of the primary fields of research since the inception of modern electronic technology. Although computers with general-purpose features offer the most substantial uses for digital electronics, the research of arithmetic circuits has typically concentrated on implementations for these devices. Computing arithmetic must have accessibility, compact size and ease of use, high efficiency, affordability, and low energy. Full adders are an adaptable aspect that is mainly employed in multiplication and addition algorithms as the fundamental interpreting elements. Adders are frequently employed in Very Large-Scale Integration (VLSI) functions for issues like Arithmetic Logic Unit (ALU) construction, address calculation in computers, multiplications, and more. Full adders constitute an effective fundamental element and essential aspect for multiple systems prevalent in VLSI and Digital Signal Processor (DSP) programs. The single-bit proposed full adder circuit and multi-layer perceptron-based full adder circuit are imposed on the design of the modular multiplier unit to verify the functionality as well as the performance of large bit size architectures. The performance characteristics of the MLP-based modular multiplier architecture, such as dynamic power dissipation (18.3%), Figure of Merit (15.7%), and Energy Delay Product (15.5%), are improved over the PFA-based modular multiplier architecture."

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