MUMBAI, India, Oct. 31 -- Intellectual Property India has published a patent application (202441033557 A) filed by Parthasarathi P; K. Sathiskumar; T. Janani; and P. Sathishkumar, Namakkal, Tamil Nadu, on April 27, 2024, for 'dynamic routing and traffic optimization mechanisms for network-on-chip architectures.'
Inventor(s) include Parthasarathi P; K. Sathiskumar; T. Janani; and P. Sathishkumar.
The application for the patent was published on Oct. 31, under issue no. 44/2025.
According to the abstract released by the Intellectual Property India: "Network-on-chip (NoC) architectures have emerged as a promising solution for on-chip communication in modern multi-core and many-core systems. NoCs provide scalable and efficient communication infrastructures by employing a network of interconnected routers to facilitate data exchange among processing elements (PEs) or cores. In a typical NoC architecture, each PE is connected to one or more routers, and communication between PEs is facilitated through packet-switched communication over the NoC. One of the critical challenges in NoC design is the efficient routing of packets across the network to ensure low latency, high throughput, and minimal power consumption. Traditional routing algorithms in NoCs often rely on static routing tables or deterministic algorithms, which may not adapt well to changing traffic patterns or network conditions. As a result, these approaches may lead to suboptimal performance or congestion in the NoC."
Disclaimer: Curated by HT Syndication.
