MUMBAI, India, Oct. 11 -- Intellectual Property India has published a patent application (202441027976 A) filed by Gupta, Nitin, Bangalore, Karnataka, on April 4, 2024, for 'digital phase-locked loop circuit and a method thereof.'
Inventor(s) include Gupta, Nitin.
The application for the patent was published on Oct. 10, under issue no. 41/2025.
According to the abstract released by the Intellectual Property India: "The present disclosure relates to a digital phase-locked loop (PLL) circuit (100). The digital PLL circuit includes a phase frequency detector (102) configured to compare a phase difference between an input reference signal and a feedback signal from a current controlled oscillator, and generate a plurality of signals. An error to digital convertor (104) electrically connected to the phase frequency detector (102) and configured to convert the plurality of signals into a plurality of digital signals. A digital controller (106) electrically connected to the error to digital convertor (104), and configured to process and convert the plurality of digital signals into a plurality of current signals. A current controlled oscillator (108) electrically connected to the digital controller (106), and configured to receive the plurality of current signals from the digital controller (106) and control a phase of the feedback signal to synchronize with a phase of the input reference signal."
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