Intellectual Property India Publishes Patent Application for 'Differential Latch-Type Sense Amplifier With Skewed Reference Path Forrobust Low-Power Sram Read Operation' Filed by B V Raju Institute Of Technology; and Pavankumar Bikki

MUMBAI, India, Jan. 2 -- Intellectual Property India has published a patent application (202541125587 A) filed by B V Raju Institute Of Technology; and Pavankumar Bikki, Narsapur, Telangana, on Dec. 12, 2025, for 'differential latch-type sense amplifier with skewed reference path forrobust low-power sram read operation.'

Inventor(s) include Pavankumar Bikki; K Manjusha; B Kranthi Kumar; K Ananda Kumar; and K. Madhavarao.

The application for the patent was published on Jan. 2, under issue no. 01/2026.

According to the abstract released by the Intellectual Property India: "Nowadays, sense amplifiers are critical in modern static random access memory's(SRAM) because they reliably detect and amplify very small voltage differences on highly capacitive bit-lines, enabling fast and accurate read operations even at low supply voltages and nanoscale nodes. Hence, a differential latch-type sense amplifier with an embedded skewed reference path is presented for high-speed, low-power SRAM read operations. The design consists of a cross coupled CMOS latch, gated at the top by a PMOS head transistor and at the bottom by an NMOS enable device, ensuring dynamic operation with reduced static current. Bit-lines BL and BLB are connected to the latch through pass transistors, isolating the large bit-line capacitances while developing a small differential at internal nodes during a read. A skewed reference branch, implemented using asymmetrically sized NMOS devices and a controllable middle node, introduces a deliberate offset that improves sensing robustness against process, voltage, and temperature variations. Dedicated control signals coordinate activation of the latch and reference path, enabling reliable and energy efficient full swing output development from small input differentials. The design strongly influences the minimum operating voltage, access time, and power consumption of the memory. Further, impacting overall system performance and energy efficiency in current low power, high density applications."

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