MUMBAI, India, Jan. 9 -- Intellectual Property India has published a patent application (202541112328 A) filed by Dr. P. Sasireka; Dr. M. Gomathi; S. Sharon Sweeti; and S. A. Engineering college, Chennai, Tamil Nadu, on Nov. 17, 2025, for 'design of a high-performance counter circuit using quantum dot cellular automata tool.'
Inventor(s) include Dr. P. Sasireka; Dr. M. Gomathi; and S. Sharon Sweeti.
The application for the patent was published on Jan. 9, under issue no. 02/2026.
According to the abstract released by the Intellectual Property India: "The scaling of electronic devices to the Nano scale has driven interest in Quantum-dot Cellular Automata (QCA) as a potential alternative to traditional CMOS technology for future digital circuits. This invention presents an efficient design for an asynchronous counter using D Flip- Flops (DFFs) within the QCA paradigm, addressing critical challenges in speed, area, and power consumption at the Nano scale. The asynchronous counter, a fundamentaVbuilding block in sequential logic circuits, is optimized to leverage the parallelism and low-power characteristics inherent in QCA. QCA's unique ability to encode binary information through the arrangement of charge configurations in quantum dots ensures minimal delay and scalability. By optimizing the placement and interaction of QCA cells, the proposed design achieves superior performance over conventional CMOS-based counterparts, particularly in terms of switching speed and energy efficiency. The asynchronous counter utilizes a divide-by-two concept, where the input clock frequency is divided by two, yielding a 2-bit and 3-bit counter. Simulation results using the QCA Designer Tool demonstrate the feasibility of the proposed design for Nano scale applications, highlighting its potential in high-performance and low-power digital sy ste m s. By designing and simulating the counter circuit using the QCA Designer tool, this project evaluates key performance metrics such as area efficiency, energy consumption, and latency. The proposed design is optimized to reduce the number of QCA cells, wire crossings, and majority gates, resulting in improved scalability and reliability. Comparative analysis with existing CMOS and QCA- based designs highlights the superior efficiency of the proposed counter in terms of speed and power efficiency. The implementation of QCA technology in sequential circuits contributes to next-generation Nano electronics devices, aligning with Sustainable Development Goal 9 (Industry, Innovation, and Infrastructure) by fostering advancements in electronics and digital infrastructure. This research not only advances QCA circuit design but also lays the groundwork for more complex and energy-efficient computing architectures, paving the way for the future of ultra-low-power Nano computing."
Disclaimer: Curated by HT Syndication.
