MUMBAI, India, May 29 -- Intellectual Property India has published a patent application (202641043549 A) filed by Hindusthan College Of Engineering And Technology, Coimbatore, Tamil Nadu, on April 6, for 'design and implementation of a stage pipelined risc v processor core using cadence digital design flow.'
Inventor(s) include Dr. N. J. R. Muniraj; R. Arunprasath; R. Logeshwaran; S. Someshvaran; V. Vignesh; and J. Aagash.
The application for the patent was published on May 29, under issue no. 22/2026.
According to the abstract released by the Intellectual Property India: "This invention describes a high-performance, hardware-efficient 5-stage pipelined RISC-V processor core that is made as an ASIC using 90nm CMOS technology. The processor's target frequency is 200 MHz, and it uses instruction-level parallelism to execute operations across five stages: Instruction Fetch (IF), Jnstrucliu11 Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). It replaces slow, non-pipelined execution with a parallel architecture and adds Hazard Detection and Forwarding modules to maintain high throughput and correctness. Using Cadence tools, the whole RTL-to-GDSII flow was done with: * Simulation in NC-Launch. * Synthesis in Genus. * Physical Design (CTS, Placement, Routing) in Innovus. * Final GDSII generation completed. The design gets a positive setup slack of0.007 ns, which makes sure that timing closure is strong while area and power use are kept to a minimum. The final post-layout results are: * Total Area: 5560.187 ~-tm'. * Total Power Consumption: 1.09248 mW. * Total Instances: 569 logic gates. * Routing Overflow: 0.00% H and 0.00% V. The invention is useful for high-speed embedded systems, Edge computing, industrial automation, and low-power digital signal processing."
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