Intellectual Property India Publishes Patent Application for 'Design And Implementation Of A Modified Carry Select Adder On Cyclone III FPGA' Filed by Srinivasa Ramanujan Institute Of Technology; Dr. K. Dadasikandar; J. Haritha; U. Pavitra; and K. Balaji

MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641050118 A) filed by Srinivasa Ramanujan Institute Of Technology; Dr. K. Dadasikandar; J. Haritha; U. Pavitra; and K. Balaji, Ananthapuramu, Andhra Pradesh, on April 20, for 'design and implementation of a modified carry select adder on cyclone iii fpga.'

Inventor(s) include Srinivasa Ramanujan Institute Technology; Dr. K. Dadasikandar; J. Haritha; U. Pavitra; and K. Balaji.

The application for the patent was published on May 1, under issue no. 18/2026.

According to the abstract released by the Intellectual Property India: "In modern digital systems, arithmetic operations play a crucial role in determining overall performance, especially in Digital Signal Processing (DSP) applications. Among these operations, addition is the most fundamental and frequently used operation, significantly affecting system speed and efficiency. This project presents the design and implementation of a high-speed Carry Select Adder (CSLA) using Parallel Prefix Adder (PPA) techniques to improve performance. The conventional Carry Select Adder reduces propagation delay by precomputing sum values for different carry inputs, but it suffers from increased area and power consumption. To overcome these limitations, the proposed design integrates parallel prefix structures such as Kogge-Stone Adder (KSA) and Brent-Kung Adder (BKA), which enhance the speed of carry computation through parallel processing. Additionally, optimization techniques are applied to reduce hardware complexity, delay, and power consumption. The proposed architecture is implemented using Verilog Hardware Description Language (HDL) and synthesized on FPGA using Quartus II tools. Simulation and performance analysis are carried out using ModelSim. The results demonstrate that the proposed CSLA design achieves improved speed, reduced power consumption, and optimized area compared to conventional adder designs. This work is suitable for high-performance applications such as DSP systems, microprocessors, and real-time signal processing, where speed and efficiency are critical. The proposed design also contributes towards energy-efficient hardware development, supporting sustainable and advanced digital system design."

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