Intellectual Property India Publishes Patent Application for 'Design and Analysis of PLL Components in 45 nm CMOS: Optimized PFD, CP, VCO, and Dividers' Filed by P A Nageswara Rao; M Harshith Mouli; Gurugubelli Manisha; Terukuti Tulasi Ram; Ati Venkata Sudhindra Kumar; and Venkatesh Seerapu

MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641048603 A) filed by P A Nageswara Rao; M Harshith Mouli; Gurugubelli Manisha; Terukuti Tulasi Ram; Ati Venkata Sudhindra Kumar; and Venkatesh Seerapu, Visakhapatnam, Andhra Pradesh, on April 16, for 'design and analysis of pll components in 45 nm cmos: optimized pfd, cp, vco, and dividers.'

Inventor(s) include P A Nageswara Rao; M Harshith Mouli; Gurugubelli Manisha; Terukuti Tulasi Ram; Ati Venkata Sudhindra Kumar; and Venkatesh Seerapu.

The application for the patent was published on May 1, under issue no. 18/2026.

According to the abstract released by the Intellectual Property India: "Design and analysis of Phase-Locked Loop (PLL) components in 45 nm CMOS technology are carried out, includ ing the Phase-Frequency Detector (PFD), Charge Pump (CP), Voltage-Controlled Oscillators (VCOs), and frequency dividers. An optimized PFD with reduced transistor count (22T to 18T) is proposed to improve area and power efficiency while maintaining accurate phase detection. The Charge Pump is designed to ensure proper current matching and stable operation. Ring VCO and Current-Starved VCO are implemented and comparatively analyzed in terms of frequency range, power consumption, and performance. Frequency dividers with division ratios of 2, 3, 4, 16, and 48 are developed to enable flexible frequency scaling. Simulation results demonstrate improved efficiency, reduced power consumption, and reliable operation, making the proposed designs suitable for low-power, high-speed CMOS frequency synthesis applications."

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