MUMBAI, India, Feb. 6 -- Intellectual Property India has published a patent application (202541122327 A) filed by Nandha Engineering College, Erode, Tamil Nadu, on Dec. 5, 2025, for 'design a gate driver malfunction detection and protection circuit for ups inverter.'
Inventor(s) include R Vijayalakshmi; S Mathankumar; S Prasath; and S Sanjay.
The application for the patent was published on Feb. 6, under issue no. 06/2026.
According to the abstract released by the Intellectual Property India: "The present invention relates to a gate driver malfunction detection and protection circuit for use in uninterruptible power supply (UPS) inverters. The invention provides a hardware-based solution capable of detecting abnormal operation of gate driver circuits controlling power semiconductor devices such as MOSFETs or IGBTs. The circuit continuously monitors the gate voltage of each switching device and compares it with the expected pulse-width modulation (PWM) control signal to identify faults such as missing gate pulses, stuck-high or stuck-low driver outputs, and shoot-through conditions. A cross-conduction detection circuit prevents simultaneous conduction of high-side and low-side switches, while an overcurrent or desaturation detection stage senses short-circuit or overload events. Fault signals generated by these detection blocks are processed through a logic and latch circuit that disables the gate driver output within microseconds, thereby protecting the inverter and DC link from damage. The fault status is cornm1micated to the controller_ via an opto-isolated feedback cha*mel for indication and system shutdown. The proposed circuit offers fast, independent, and reliable protection against gate driver failures, enhances inverter safety, and ensures stable operation of singlephase and three-phase. UPS systems."
Disclaimer: Curated by HT Syndication.
