Intellectual Property India Publishes Patent Application for 'Delay-Locked Loop Offset Calibration And Correction' Filed by Advanced Micro Devices, Inc.

MUMBAI, India, Aug. 22 -- Intellectual Property India has published a patent application (202517053788 A) filed by Advanced Micro Devices, Inc., Santa Clara, U.S.A., on June 3, for 'delay-locked loop offset calibration and correction.'

Inventor(s) include Chu, Andy Huei; Gopalakrishnan, Karthik; and Jayaraman, Pradeep.

The application for the patent was published on Aug. 22, under issue no. 34/2025.

According to the abstract released by the Intellectual Property India: "A clocking circuit is provided using a master delay-locked loop (DLL) and a slave DLL. A master DLL code indicates a delay adjustment made at a master DLL. A delay of a slave DLL is adjusted based on the master DLL code. A replica phase detector at the slave DLL is temporarily enabled during an interface idle period. A slave DLL code is determined, and a configuration value is determined based on the slave DLL code to the master DLL code.The replica phase detector is then disabled."

The patent application was internationally filed on Dec. 07, 2023, under International application No.PCT/US2023/082979.

Disclaimer: Curated by HT Syndication.