MUMBAI, India, Oct. 31 -- Intellectual Property India has published a patent application (202411028223 A) filed by Nvidia Corporation, Santa Clara, U.S.A., on April 5, 2024, for 'clock gating of free index flop arrays.'
Inventor(s) include Mugu, Anil; Chakilam, Shanthan; Lakshita; Rangateja, Raavikrindi; and Patel, Ronit Vijaybhai.
The application for the patent was published on Oct. 31, under issue no. 44/2025.
According to the abstract released by the Intellectual Property India: "A system is described to include a first storage element having a plurality of data storage locations, a second storage element having an array of bits indicating an availability for a corresponding data storage location in the plurality of data storage locations, and a control circuit. The control circuit may include at least a first switching element coupled to a first set of bits in the array of bits, the at least a first switching element selectively enables the first set of bits to be read or written in response to being activated by a first clock gating signal as well as at least a second switching element coupled to a second set of bits in the array of bits, the at least a second switching element selectively enables the second set of bits to be read or written in response to being activated by a second clock gating signal."
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