MUMBAI, India, July 11 -- Intellectual Property India has published a patent application (202541060955 A) filed by CVR College Of Engineering, Hyderabad, Telangana, on June 26, for 'asymmetric channel fin-tfet with graphene conduction path and gaassb/gasb heterojunction for enhanced dc and ac response..'
Inventor(s) include Dr. P. Ramesh.
The application for the patent was published on July 11, under issue no. 28/2025.
According to the abstract released by the Intellectual Property India: "The invention discloses an asymmetric channel Fin-TFET incorporating a graphene conduction path, GaSb source, and GaAsSb drain with a GaAsSb/GaSb heterojunction at the tunneling junction. The device features a tapered, non-uniform channel structure that is wider near the source and narrower near the drain, strategically enhancing band-to-band tunneling while suppressing leakage and ambipolar current. The graphene channel ensures high mobility and strong gate control, while the staggered band alignment of the source heterojunction boosts tunneling efficiency. A high-k dielectric and wrap-around gate structure further optimize electrostatics. Simulation and theoretical analyses indicate significant improvements in ON-current, subthreshold swing, and AC performance metrics compared to conventional TFETs. This design is ideal for low-power, high-speed applications in RF, logic, and sensor technologies."
Disclaimer: Curated by HT Syndication.
