MUMBAI, India, May 29 -- Intellectual Property India has published a patent application (202641035530 A) filed by IIITB COMET Foundation; International Institute Of Information Technology, Bangalore; and Indian Institute Of Technology Roorkee, Bengaluru, Karnataka, on March 24, for 'architecture for fpga-based acceleration of pdsch processing.'
Inventor(s) include Samudrala Soujanya; Harsha Rudramuniyappa; Prem Singh; and Ekant Sharma.
The application for the patent was published on May 29, under issue no. 22/2026.
According to the abstract released by the Intellectual Property India: "An FPGA-based architecture is disclosed for accelerating a 5G New Radio (5G-NR) Physical Downlink Shared Channel (PDSCH) processing chain in a base station. Architecture reduces processing latency and improves resource utilization relative to conventional implementations that are unable to satisfy stringent timing constraints for low-latency operation. The architecture employs an optimized data-bus arrangement, including a 128-bit data width up to a rate-matching stage and a 96-bit data width for subsequent procedures. Furthermore, it employs a modular multi-IP approach, where the PDSCH chain is realized using specialized functional blocks, including Transport Block CRC Attachment IP, Code Block Segmentation IP, Code Block CRC Attachment IP, LDPC configuration IP and LDPC post IP, Null bit filter IP and SRI IP, Concatenation IP, Golden sequence generator IP, and Modulation IP. In an implementation, the architecture is configured to generate the first modulated symbols within about 32 microseconds while maintaining efficient FPGA resource usage, and improved throughput and energy efficiency."
Disclaimer: Curated by HT Syndication.
