Intellectual Property India Publishes Patent Application for 'An Interface Circuit Using Mirrored Current Feedback To Reduce Input Impedance' Filed by Power Integrations, Inc.

MUMBAI, India, Nov. 7 -- Intellectual Property India has published a patent application (202514032629 A) filed by Power Integrations, Inc., San Jose, U.S.A., on April 2, for 'an interface circuit using mirrored current feedback to reduce input impedance.'

Inventor(s) include Takayasu Sato.

The application for the patent was published on Nov. 7, under issue no. 45/2025.

According to the abstract released by the Intellectual Property India: "An interface circuit using mirrored current feedback to reduce input impedance is disclosed herein. According to the teachings herein, the interface circuit includes a current mirror and an input circuit path. Shunt feedback via a return circuit path provides a mirrored current to an interface input thereby reducing an input impedance of the interface circuit. By virtue of shunt feedback, the input impedance of the interface circuit is reduced relative to the impedance of the input circuit path. In this manner, input impedance of the interface circuit may be reduced without changing the impedance of the input circuit path."

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