MUMBAI, India, Jan. 23 -- Intellectual Property India has published a patent application (202511125795 A) filed by Delhi Technological University, New Delhi, on Dec. 12, 2025, for 'an automated verification system for system-on-chip designs and method thereof.'
Inventor(s) include Kapoor, Rajiv; Dash, Ajay; Kapoor, Aarchishya; and Kapoor, Ruchirangad.
The application for the patent was published on Jan. 23, under issue no. 04/2026.
According to the abstract released by the Intellectual Property India: "An automated verification system (100) and method (200) for System-on-Chip (SoC) modules are disclosed. The system (100) includes a generation layer module (110) to generate design artifacts comprising module descriptions, code snippets, and schematic suggestions based on a user input and design requirements; a verification layer module (120) comprising structured data sources that may include a relational database, a semantic vector store, and a programmable interface, each configured for validating the generated design artifacts; a simulation or reinforcement learning layer module (130) adapted to test functional behaviour of SoC modules for generating runtime verification evidence; and a Dempster-Shafer Theory (DST) engine (140) to receive a verification confidence value from each of the generation layer module (110), the verification layer module (120), and the simulation or reinforcement learning layer module (130), and assign belief masses and apply Dempster's rule of combination to generate a unified verification decision and associated confidence metric."
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