MUMBAI, India, April 17 -- Intellectual Property India has published a patent application (202611021042 A) filed by Ajay Kumar Garg Engineering College, Ghaziabad, Uttar Pradesh, on Feb. 23, for 'an ai-based arc fault detection system for low-voltage electrical distribution lines and working method thereof.'
Inventor(s) include Deevanshu Chauhan; Rudra; Mr. Ravindra Kumar; and Mr. Gaurav Srivastava.
The application for the patent was published on April 17, under issue no. 16/2026.
According to the abstract released by the Intellectual Property India: "The present invention discloses an AI-based arc fault detection system and working method thereof for low-voltage electrical distribution lines. The system comprises current and voltage sensors, high-speed signal conditioning and digitization circuitry, an embedded processing unit, and a trained one-dimensional convolutional neural network configured for real-time arc fault classification. High-frequency electrical signals are acquired, processed, and transformed into a fault-signature matrix, which is analyzed using embedded neural inference to distinguish hazardous arc faults from normal load transients with high accuracy and low latency. Upon detection of an arc fault, a solid-state relay is actuated to rapidly isolate the faulted circuit, thereby preventing electrical fire hazards. The invention achieves detection latency below 100 milliseconds, significantly reduces nuisance tripping, and improves sensitivity toward low-current serial arcs. The system is compact, energy-efficient, and suitable for deployment in residential, industrial, renewable energy, and smart grid electrical infrastructures."
Disclaimer: Curated by HT Syndication.
