MUMBAI, India, Jan. 9 -- Intellectual Property India has published a patent application (202511115791 A) filed by Ajay Kumar Garg Engineering College, Ghaziabad, Uttar Pradesh, on Nov. 23, 2025, for 'ai-integrated system for simulation and predictive modeling of flip-flop digital circuits and working method thereof.'
Inventor(s) include Pushkar Singhal; Pushpendra Singh; Priyansi; Ramakant; Dr. Inderjeet Kaur; and Ms. Shraddha Pandey.
The application for the patent was published on Jan. 9, under issue no. 02/2026.
According to the abstract released by the Intellectual Property India: "The present invention discloses an AI-integrated system and method for simulation and predictive modeling of flip-flop-based digital circuits. The system combines a hardware-representative logic layer with configurable SR, D, JK, and T flip-flop models, a dual-mode simulation orchestration kernel, and an AI ensemble comprising decision-tree predictors, temporal neural networks, and probabilistic estimators. The invention enables generation of accurate timing behavior, toggling-state prediction, and metastability-risk estimation using trace-driven machine-learning inference. A closed-loop architecture allows AI-derived insights to dynamically guide high-fidelity simulation, targeted test-vector generation, and hotspot escalation, thereby improving detection of corner-case timing violations. The method includes modeling of logic primitives, simulation of sequential states, AI-based analysis, and annotated waveform visualization. The system provides enhanced efficiency, predictive accuracy, and industrial applicability in digital-design verification under varying clock, load, and process conditions."
Disclaimer: Curated by HT Syndication.
