MUMBAI, India, Jan. 9 -- Intellectual Property India has published a patent application (202511115796 A) filed by Ajay Kumar Garg Engineering College, Ghaziabad, Uttar Pradesh, on Nov. 23, 2025, for 'ai-integrated system for generative optimization of intelligent 8-bit arithmetic logic units and working method thereof.'
Inventor(s) include Nishchay Agrawal; Naman Hari Garg; Nitin Yadav; Dr. Inderjeet Kaur; and Ms. Shraddha Pandey.
The application for the patent was published on Jan. 9, under issue no. 02/2026.
According to the abstract released by the Intellectual Property India: "The present invention discloses an AI-integrated system for generative optimization of intelligent 8-bit Arithmetic Logic Units (ALUs). The system comprises a traditional 8-bit ALU operatively coupled with a lightweight Generative Artificial Intelligence (GenAI) controller configured to analyze operand-opcode patterns, predict optimal execution paths, and dynamically regulate internal logic activation. A feedback-driven learning module continuously monitors real-time performance metrics, enabling adaptive gating, reduced switching activity, predictive fault detection, and autonomous performance refinement. The GenAI controller selectively activates arithmetic or logical sub-units and suppresses unused blocks, thereby decreasing power consumption and computation latency. The invention provides a self-optimizing hardware architecture capable of real-time learning and scalable deployment in embedded controllers, IoT devices, edge processors, and ASIC/FPGA platforms. The system significantly enhances efficiency, reliability, and throughput compared to conventional deterministic ALUs."
Disclaimer: Curated by HT Syndication.
