MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641050439 A) filed by Madhankumar C; Ms. Payal Shah; Dr. Kruti P. Thhakore; Rahulkumar Jasamatbhai Thumar; G. Shasikala; Dr. J. Raja; and Dr. K. Sedhuramalingam, Pollachi, Tamil Nadu, on April 21, for 'ai-assisted ultra-low power adaptive vlsi architecture for high performance and energy-efficient computing.'
Inventor(s) include Ms. Payal Shah; Dr. Kruti P. Thhakore; Rahulkumar Jasamatbhai Thumar; G. Shasikala; Dr. J. Raja; and Dr. K. Sedhuramalingam.
The application for the patent was published on May 1, under issue no. 18/2026.
According to the abstract released by the Intellectual Property India: "AI-Assisted Ultra-Low Power Adaptive VLSI Architecture for High Performance and Energy-Efficient Computing Abstract The rapid growth of data-intensive applications, including artificial intelligence, edge computing, and Internet of Things (IoT), has significantly increased the demand for high-performance yet energy-efficient hardware systems. Conventional VLSI architectures often struggle to balance computational throughput with power constraints, especially in resource-limited environments. This research proposes an innovative AI-assisted ultra-low power adaptive VLSI architecture designed to dynamically optimize performance and energy consumption in real time. The proposed system integrates machine learning models within the hardware control loop to monitor workload characteristics, predict computational demand, and adapt circuit parameters such as voltage scaling, clock frequency, and power gating. By leveraging intelligent decision making mechanisms, the architecture enables fine-grained control over processing elements, reducing unnecessary power dissipation while maintaining high processing efficiency. The design incorporates adaptive logic blocks, reconfigurable interconnects, and energy-aware scheduling units to support diverse workloads with minimal overhead. Furthermore, the architecture utilizes advanced techniques such as dynamic voltage and frequency scaling (DVFS), near-threshold computing, and hardware-level neural predictors to achieve significant improvements in power efficiency. Simulation results demonstrate that the proposed system reduces power consumption by up to 35-50% compared to conventional static VLSI designs, while maintaining or enhancing computational performance. This work contributes to the advancement of intelligent hardware design by bridging the gap between AI-driven optimization and low-power VLSI systems. The proposed architecture is highly suitable for next-generation applications such as wearable devices, autonomous systems, and smart embedded platforms, where energy efficiency and real-time performance are critical."
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