MUMBAI, India, Jan. 9 -- Intellectual Property India has published a patent application (202541133729 A) filed by Indian Institute Of Technology, Hyderabad, Telangana, on Dec. 30, 2025, for 'a system and method for reinforcement learning-based dynamic frequency scaling in a field-programmable gate array based platform.'
Inventor(s) include Ratnala Vinay; Kartik Laad; Parveen Nisha; and Amit Acharyya.
The application for the patent was published on Jan. 9, under issue no. 02/2026.
According to the abstract released by the Intellectual Property India: "The present subject matter relates to a system and method for reinforcement learning based dynamic frequency scaling in a field programmable gate array based platform. The system 100 includes a custom hardware intellectual property (IP) core 101 implemented in programmable logic, whose operational performance scales with clock frequency. A programmable multi-output clock generation module 102 produces multiple discrete clock signals from a single stable reference clock, which are managed by a clock wrapper module 103. A PL-side clock controller 104 dynamically selects and applies a selected clock signal to the custom hardware IP core 101 during runtime. Real-time performance metrics are measured by a performance monitoring and feedback mechanism 105 and transmitted to a processing system 105 executing a reinforcement learning engine 107. Based on the received feedback, the reinforcement learning engine 107 determines an operating clock frequency that optimizes a power-performance tradeoff and generates frequency control commands. The reinforcement learning engine 107, performance monitoring and feedback mechanism 105, and PL-side clock controller 104 collectively form a closed-loop adaptive control system enabling real-time dynamic adjustment of programmable logic operating frequency."
Disclaimer: Curated by HT Syndication.
