MUMBAI, India, Feb. 27 -- Intellectual Property India has published a patent application (202641017072 A) filed by Rajesh Kolagatla, Hyderabad, Telangana, on Feb. 16, for 'a system and method for parallel numerical computation using a binary encoding architecture.'
Inventor(s) include Rajesh Kolagatla.
The application for the patent was published on Feb. 27, under issue no. 09/2026.
According to the abstract released by the Intellectual Property India: "A system and method for parallel numerical computation using a binary encoding architecture is disclosed. The system includes a processor and memory coupled thereto, the memory storing instructions that cause the processor to: receive numeric operands in inputs; encode operands into 4-bit chunks per 4-bit split encoding (each chunk a digit or reserved symbol); compute in parallel on the 4-bit chunks for integer and floating-point arithmetic; execute memory-variable matching on chunks to determine equality and relations; perform multiplication via parallel iterative addition across chunks; perform floating-point computation by scaling mantissa to integer, executing integer arithmetic, reinserting the decimal point, and deleting trailing zeros; allocate memory dynamically based on a selectable number of 4-bit chunks per word length; and output results via a user interface to a user device, with results in selected binary encoding comprising the 4-bit split encoding, 1-bit sign indicator, or combination based on usage requirement."
Disclaimer: Curated by HT Syndication.
