MUMBAI, India, Feb. 27 -- Intellectual Property India has published a patent application (202541131908 A) filed by Dr. Isaivani Mariyappan; Suresh Kannan S; Anuja K S; and Saranya V, Madurai, Tamil Nadu, on Dec. 26, 2025, for 'a scalable multi-processor system-on-chip with adaptive inter-core communication architecture.'
Inventor(s) include Dr. Isaivani Mariyappan; Suresh Kannan S; Anuja K S; and Saranya V.
The application for the patent was published on Feb. 27, under issue no. 09/2026.
According to the abstract released by the Intellectual Property India: "A scalable multi-processor system-on-chip (MPSoC) with an adaptive inter-core communication architecture is disclosed. The system integrates a plurality of processing cores on a single semiconductor substrate and employs an adaptive communication fabric to dynamically manage data transfer among the processing cores. The adaptive architecture monitors runtime communication conditions and adjusts routing paths, bandwidth allocation, and power usage to reduce latency, alleviate congestion, and improve energy efficiency. The proposed MPSoC supports heterogeneous processing elements, quality-of-service requirements, and scalable expansion to large core counts. The invention is suitable for high-performance embedded systems, real-time computing, artificial intelligence processing, and advanced multicore applications."
Disclaimer: Curated by HT Syndication.
