MUMBAI, India, June 16 -- Intellectual Property India has published a patent application (202611054227 A) filed by Indian Institute Of Technology, New Delhi, on April 28, for 'a method and a system for mitigating errors in quantum computations.'
Inventor(s) include Sivasubramani, Santhosh.
The application for the patent was published on June 5, under issue no. 23/2026.
According to the abstract released by the Intellectual Property India: "Disclosed herein is a method performed by a computing system for mitigating errors in quantum computations. The method includes creating (902) quantum circuit data based on receiving a quantum circuit description and associated execution parameters. The quantum circuit data represents structural characteristics of a quantum computation. The method further includes determining (904) circuit characteristic information by correlating the quantum circuit data with predefined circuit analysis rules. Further, the method includes generating (906) noise influence information by correlating the circuit characteristic information with noise characterization data of quantum hardware, the noise influence information indicating an estimated contribution of noise during execution. Further, the method includes selecting (908) a mitigation strategy based on correlating the circuit characteristic information with the noise influence information to reduce the identified noise influence. Furthermore, the method includes generating (910) an error mitigated quantum computation result based on applying the selected mitigation strategy to the quantum circuit data."
Disclaimer: Curated by HT Syndication.
