MUMBAI, India, May 1 -- Intellectual Property India has published a patent application (202641049588 A) filed by Seshadri Rao Gudlavalleru Engineering College; Ms. V. Priya Darshini; Ch. Sai Krishna; D. Elisha; B. Lokesh; and A. Srihari, Gudivada, Andhra Pradesh, on April 18, for 'a low power carry look-ahead decimal adder for high-speed decimal arithmetic operations.'
Inventor(s) include Seshadri Rao Gudlavalleru Engineering College; Ms. V. Priya Darshini; Ch. Sai Krishna; D. Elisha; B. Lokesh; and A. Srihari.
The application for the patent was published on May 1, under issue no. 18/2026.
According to the abstract released by the Intellectual Property India: "Decimal arithmetic plays a crucial role in modern digital systems where accurate base-10 computation is required. Conventional decimal adders suffer from propagation delay due to sequential carry generation, which affects overall system performance. To overcome these limitations, the present invention proposes a low-power Carry Look-Ahead Decimal Adder (CLDA) that generates carry signals in parallel using propagate and generate logic. The system utilizes Binary Coded Decimal (BCD) representation to ensure accurate decimal computation and incorporates correction logic to maintain valid output. The proposed design is implemented using Verilog Hardware Description Language (HDL) and synthesized on FPGA platforms. The architecture supports multiple digit configurations and enables efficient hardware utilization. This invention significantly reduces propagation delay, improves computational speed, and optimizes power consumption, making it suitable for modern high-performance digital systems. Keywords: Carry Look-Ahead Decimal Adder; Binary Coded Decimal (BCD); Low Power Design; High-Speed Arithmetic; Parallel Carry Generation; FPGA Implementation; Verilog HDL; Propagate and Generate Logic; Decimal Arithmetic Circuits; Digital System Design; Hardware Optimization; Multi-Digit Adder Architecture."
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