MUMBAI, India, Feb. 13 -- Intellectual Property India has published a patent application (202521133639 A) filed by Teena Soni; Anil Kumar; Nikhil Agrawal; Deepak Mishra; Himanshu Gupta; Ayushi Jaiswal; and Aditya Tiwari, Jabalpur, Madhya Pradesh, on Dec. 30, 2025, for 'a hardware-optimized two-channel quadrature mirror filter bank system for signal processing and its method threreof.'
Inventor(s) include Teena Soni; Anil Kumar; Nikhil Agrawal; Deepak Mishra; Himanshu Gupta; Ayushi Jaiswal; and Aditya Tiwari.
The application for the patent was published on Feb. 13, under issue no. 07/2026.
According to the abstract released by the Intellectual Property India: "The invention relates to a hardware-optimized two-channel quadrature mirror filter bank that achieves low-complexity, multiplierless realization with improved speed and power efficiency. The system first represents prototype filter coefficients in canonical signed digit form and processes them in a working matrix, where variable-length bit patterns are exhaustively scanned in horizontal, vertical, and diagonal directions. A benefit-driven selection of recurring patterns is then performed, iteratively replacing the most cost-effective subexpressions to minimize the number of unique addition operations while preserving filter characteristics. The optimized coefficients are implemented using dedicated shift-and-add blocks feeding a hierarchical carry-save adder tree, which accumulates partial sums in parallel and reduces critical path delay. The prototype filter realizes analysis low-pass and high-pass branches, followed by downsampling, and a corresponding synthesis section including upsampling and reconstruction addition, thereby enabling efficient, real-time, two-channel QMF operation on FPGA and ASIC platforms."
Disclaimer: Curated by HT Syndication.
