MUMBAI, India, May 29 -- Intellectual Property India has published a patent application (202611048997 A) filed by Noida Institute Of Engineering & Technology, Greater Noida, Uttar Pradesh, on April 17, for 'a cache-aware linked list structure for memory optimization.'
Inventor(s) include Sovers Singh Bisht; and Dr. Sakshi Kumar.
The application for the patent was published on May 29, under issue no. 22/2026.
According to the abstract released by the Intellectual Property India: "A cache-aware linked list structure is disclosed comprising a list controller (101), a head segment pointer (102), segmented nodes (103, 104), an occupancy descriptor (105), a local element slot array (106), an inter-segment link field (107), an allocator interface (108), and a tuning module (109). Multiple logical elements are stored within each segmented node to improve spatial locality during traversal. Occupancy controlled insertion, deletion, split, and merge operations preserve linked semantics while reducing pointer overhead and memory access latency, thereby optimizing processor cache utilization in dynamic data management applications."
Disclaimer: Curated by HT Syndication.
