MUMBAI, India, June 6 -- Intellectual Property India has published a patent application (202517047433 A) filed by Neo Semiconductor, Inc., San Jose, U.S.A., on May 16, for '3d cells and array structures and processes.'
Inventor(s) include Hsu, Fu-Chang.
The application for the patent was published on June 6, under issue no. 23/2025.
According to the abstract released by the Intellectual Property India: "Various 3D cells, array structures and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, an insulator surrounding a first portion of vertical bit line, a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line, and an extended portion of conductor material surrounding the continuous semiconductor layer. The memory cell structure also includes a first dielectric layer surrounding extended portion of conductor material, a first conductor layer surrounding the first dielectric layer, a second conductor layer surrounding the first conductor layer, a second dielectric layer on a top surface of the first and second conductor layers, a third dielectric layer on a bottom surface of the first and second conductor layers, a first gate on a top surface of the second dielectric layer, and a second gate on a bottom surface of the third dielectric layer."
The patent application was internationally filed on Oct. 18, 2023, under International application No.PCT/US2023/077238.
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